.J-Testr Core is at the very heart of all J-Testr functional test systems. The J-Testr Core provides a highly compact test engine that contains modular stimulation / measurement peripheral cards and the power architecture and communication architecture required to implement advanced and flexible functional test solutions.
Unique Peripheral Cards
Our unique peripheral cards are shaped to allow the direct plugging from the J-Testr Core to the Interposer in one action and require no cabling. This concept allows much improved signal losses and signal integrity issues related to cabling and interconnects present in more tradition test systems
Available functions include:
Power Supplies, Electronic Loads, Precision ADC/DAC Channels, High Seed Timer IO, Low Voltage IO (JTAG compatible), High Voltage IO (JTAG compatible), CAN/RS422/RS485, User IO (I2C, UART, SPI, PWM, Timer features), +others
Learn more about the available peripheral cards here
Internal Motherboard and System Peripheral
All J-Testr Core platforms have internal fixed system electronics that include an internal motherboard and system peripheral card that take care of all the required system functions and provide the power architecture and communication architecture to the rest of the test system.
The system electronics take care of cooling, power management, power measurement , power switching , communications interfaces, System IO resources, J-Safe Measure features, other J-Safe functions.
At the lowest level the J-Testr Core is controlled via a simple memory mapped 16-bit register sets, accessed via the ethernet port, that behaves extremely similar to a micro-controller device. This interface was designed to make any engineer with some micro-controller knowledge instantly at home.
This interface makes the J-Testr core be able to be used by any software platform with access to a socket interface. However Eiger design supports higher level drivers (function wrappers) in native ATEASY and generic DLL packages. The later DLL can be used with common plateforms like TestStand, LabVIEW, C#, C++, python and many more.
Simple and familiar Debugging
All software needs simple and effective debugging tools to speed the development process. The J-Testr Cores memory mapped 16-bit register sets are supported by the open source J-Debugr software tool which allow a 'real-time' view of all registers within the core and its peripherals.
Designed purposely to look very similar to micro-controller debugging tools and with features like time-stamped logging and color-coded actions user with any basic knowledge of micro-controllers are placed in an instantly familiar environment. Click here for more information.